Silicon

Crit-Cmpnts; ECI Ph2;

ST M Frame Contract (Provision of EEE components)

Provision of EEE components

4200018799/0/0/3

Crit-Cmpnts; ECI Ph1;

ST M Frame Contract (Provision of EEE components)

Provision of EEE components

4200018799/0/0/0

ECI; ECI Ph3 EEE326;

European Radiation Hard Power MOS Transistor for 100V-150V Range: Technology and Products Development (EEE326)

The objectives of this activity shall be to develop and demonstrate high performance packaged prototypes of European radiation hard n-chanel PowerMOS Transistor technology in the range of 100-150V.

4000107440/0/0/0

ECI; ECI Ph3 EEE316;

Development and ESCC Evaluation of a 32Mbit EEPROM (EEE316)

Development and ESCC evaluation of a radiation hardened 32Mbit EEPROM.

4000105945/0/0/1

ECI

ESCC Evaluation of ATF280F Atmel FPGA

The target of this activity is to define, manage, perform and complete the European Space Components Coordination (ESCC) evaluation of this 280Kgate FPGA device from ATMEL.

During this evaluation, the devices under test shall be extensively characterised and their margins determined in order to evaluate the capability of the ATF280F part for space applications. The evaluation of the component capabilities aims also to anticipate, as far as is possible, the component behaviour during qualification testing. As a result, during evaluation the objective shall be to overstress specific characteristics of the component concerned with a view to the detection of possible failure modes. Additionally, a detailed destructive physical analysis shall be performed to detect any design and/or construction defects which may affect the reliability of the component. All evaluation tests may in parallel indicate potential corrective improvements for reliability performance enhancement.  

420019083

LET-SME

Test Board for Dynamic Post Programming Burn-In

The Field Programmable Gate Array (FPGA) Post Programming Burn-In test philosophy is quite well mature now but the time and the cost for developing such solutions is high. Thus, only few test solutions have been developed compared to the market needs. Serma Technlogies focused on the development of two new test solutions. As one of the remaining questions about Post Programming Burn-In is the reliability of the Burn-in itself, a study to improve the monitoring of boards’ reliability could be benficial. Thus and in order to meet the Space programs needs a LET-SME activity was kicked-off with Serma Technologies, in December 2009 to develop an efficient European post-programming burn-in service for one time programmable FPGA device users. This activity looks to develop a new test solution for 2 Actel FPGA part types, namely the RTAX2000 LG624 and RTAX250S-CQ208 devices. The benefit of such a service to users is to minimise the risk of FPGA failure as programming physically alters the one-time programmable component and its quality after programming cannot be assured alone by the screening on blank parts performed by the manufacturer. The steps for developing the 2 solutions are similar, only the complexity changes.

4200022865/09/NL/VS

ECI

Development and Qualification of Radiation Hardened Serial & Parallel 4Mb EEPROM for Space Application

Serial and parallel EEPROMs are extensively used in spacecraft systems in a variety of applications for their non-volatility and in-system programmability. Since the Hitachi obsolescence announcement of its radiation tolerant EEPROM product there are not many choices left to space customers. The commercial market has long turned to FLASH based EEPROM technology to satisfy the demand for high storage capacity, low power Non Volatile Memory components. Unfortunately, most current commercial device types in conventional or FLASH EEPROM technology are very sensitive to radiation effects, both Total Dose and Single Event Effects.

The aim of this activity was to cover the development, evaluation and qualification of radiation hardened 4Mbit serial EEPROM device for space application to be manufactured on Atmel 0.18 μm CMOS AT58KRHA process in production at Atmel Rousset (F).

420019083/05/NL/FM

ECI; ECI Ph3 EEE317

Assessment and characterization of Mixed Signal Technology (EEE17)

To identify the required common design, evaluation and qualification flow of the European foundries that allow the space ASIC design a maximum portability between foundries, assembly and test houses. The survey should investigate the commonalities between the foundries and  research the degree of harmonisation that is achievable for each foundry, assembly and test house.

4000107760/0/0/0

TRP; GAD 2.06.C;

Reliability Assessment Of European Power Mosfets Phase 1 and 2

To evaluate and develop radiation hardened N- and P-channel power MOSFET devices with rated drain-source voltages between 45 V and 60V.

4000104516/0/0/2

Crit-Cmpnts; ECI Ph2

Development evaluation and qualification of a radiation hardened low-side MOSFET Driver

To develop and ESCC evaluate a radiation-hardened low side MOSFET driver for space applications.

4200022783/0/0/5

ECI

ESCC Evaluation of a 0.13 µm SiGe BiCMOS Technology

The objective of this activity is to perform the ESCC evaluation of the IHP 0.13um SG13S SiGe BiCMOS technology and so evaluate the device capabilities as required for space applications and thereby to anticipate, as far as possible, device behaviour during qualification testing and capability approval. The aim of the testing shall be to overstress the devices with a view of detecting possible failure modes. Also included is a detailed construction analysis (CA) and a check of the susceptibility of the devices to ESD. Radiation analysis testing will be covered by a parallel DLR contract with IHP (contract number: 50PS1207).

4000107989/0/0/0

No deliverables to be provided to ESCIES.

ECI

ESCC Evaluation and Qualification of a High-Speed Low Power European DAC (EEE320)

The objective of this activity is to ESCC evaluate and qualify one European source for a 12bit high speed (up to 3Gsps) and low power (<1.5W) supplied DAC. ESCC Basic Specification No. 20100 shall form the basis for the execution of this activity. The aim will be to have a European 12bit high speed and low power DAC which is EPPL and EQPL listed. In Annex 1 the requested performance requirements are presented.

4000107476/0/0/1

No deliverables to be provided to ESCIES.

TRP

Reliability testing of Commercial Available Flash memories

The aim of this activity is to assess commercial state-of-the-art flash memories and to assess the reliability of advanced memory devices for space applications. It shall identify and assess the suitability and reliability of such a technology for space applications and shall run in parallel to activity T222-016QC which is titled “Radiation Hard Memory: Radiation Testing of Candidate Memory Devices for Laplace Mission”. Activity T222-016C with EADS Astrium shall radiation test Micron NAND flash single-level cell (SLC) devices and/or 8Gb Samsung NAND flash SLC devices.

4000104985/0/0/1

No deliverables to be provided to ESCIES.

TRP

16-BIT ADC

The objective of this activity is to design, manufacture and test a standalone high speed (20 Msps) and high resolution (16 bit) ADC. The primary use of this device shall be for CMOS image sensors and also potentially any generic analog signal data acquisition e.g. from CCD image sensors. Also however, on-board atomic clocks are one of the key elements of GNSS systems that could be considered for use in high resolution instruments for Earth Observation or Space Science and Secure Telecom Applications. Several new types of clocks with better performances and requiring larger number of simultaneous high-resolution control channels will require mixed signals ICs and in particular high resolution ADCs and DACs. Apart from use as image sensors and possibly for on-board atomic clocks, an ADC device to be applicable in other high resolution instruments shall be developed as generic as possible.

4000108445/0/0/0

No deliverables to be provided to ESCIES.

TRP

Technology assessment of DRAM and advanced memory products following in from Radiation test and benchmark of commercial products against space requirements.

This activity is divided into two groups, namely Group-A and Group-B. The aim of Group-A in this activity is to assess commercial state-of-the-art DRAM memories and to assess their robustness for space applications by performing an evaluation test program (ETP) and shall focus upon determining the component performance margins for the space environment. It shall identify the current state of the art of DRAM technologies and shall assess the robustness and performance margins of these COTS devices for space applications and shall run in parallel to activity T222-016QC which is titled “Radiation Hard Memory: Radiation Testing of Candidate Memory Devices for Laplace Mission”.

The objective of the Group-B activity is to carry out the radiation assessment and technology evaluation of state of the art advanced memory technologies and devices that are of potential interest for space applications like FeRAM, MRAM, PCRAM and ferroelectric polymers due to their intrinsic robustness against radiation effects. The afore-mentioned advanced memories can offer faster access and lower power consumption compared to flash memory as well as simpler memory interface compared to DDR SDRAM.

4000104887/0/0/0

No deliverables to be provided to ESCIES.

ECI

Redesign and ESCC Evaluation of the Redesigned 4Mb EEPROM Themis

The objective of this activity is to ESCC evaluate a European source for a 4Mb EEPROM from Atmel. ESCC Basic Specification No. 20100 (AD-8) shall form the basis for the execution of this activity. The aim will be to have a European 4Mb EEPROM which is EPPL listed.

4000000000/0/0/0

No deliverables to be provided to ESCIES.

TRP

Development of a monolithic pulse-width-modulated (PWM) IC.

DC/DC Converters destined for space applications have in the past presented problems to the designers. Regarding specifically the control aspects of the DC/DC Converter, many of the problems are derived from the fact that the IC controllers used were not conceived for space applications. In general, they are up-screened parts with limited radiation test data. Tolerance to total ionizing dose may be limited and latch-up problems have been found in the past. In addition, the long term availability of the non-European products is not guaranteed with a risk of obsolescence with limited notice and control.

The objective of this activity is, therefore, the development of a Standard Pulse-Width-Modulated Integrated Circuit suitable for space applications. Such a device shall withstand at a minimum a total ionizing dose level of at least 100kRad(Si) and shall not be latch-up sensitive in the usual space radiation environment. Finally, to avoid the risk of export restrictions, the development shall be performed using a European source.

4000108411/0/0/0

No deliverables to be provided to ESCIES.

ESA

Rok Dittrich

VLSI

Rok.Dittrich@esa.int

+31 (0)7 15 65 34 82