Document Properties | |
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Feedback to: | Anastasia Pesce |
Published: | 20-04-2018 |
Public Document |
ESA / SCC Specifications for 54S Series IC's
The ESA/SCC System is OBSOLETE and is superseded by the ESCC System .
Specifications for 54S Series IC's
All specification links are to pdf files with an average file size of 1 to 2 MB.
Doc. or Spec. No. | Issue | Rev. | Specification Title |
---|---|---|---|
9201/056 MS | 2 | Quad 2-Input Positive NAND Gates, based on type 54S00 | |
9201/057 | 2 | Quad 2-Input Positive AND Gate with Open Collector Output, based on type 54S09 | |
9201/058 | 2 | Triple 3-Input Positive NAND Gate, based on type 54S10 | |
9201/059 | 2 | Dual 4-Input Positive NAND Gate, based on type 54S20 | |
9201/060 | 2 | 8-Input Positive NAND Gate, based on type 54S30 | |
9201/074 | 2 | Quad 2-Input Positive NOR Gate, based on type 54S02 | |
9201/077 | 2 | Dual 4-Input Positive NAND Gate with Open Collector Outputs, based on type 54S22 | |
9201/078 | 2 | Dual 2-Wide 2-Input AND-OR INVERT Gates, based on type 54S51 | |
9201/079 | 2 | Quadruple 2-Input Exclusive OR Gate, based on type 54S86 | |
9201/083 | 2 | Dual 5-Input Positive NOR Gate, based on type 54S260 | |
9201/112 | 2 | Positive OR Gate, based on type 54S32 | |
9202/059 | 2 | 9-Bit Odd/Even Parity Generator/Checker, based on type 54S280 | |
9203/026 | 2 | Dual D Positive Edge Triggered Flip-Flop with Preset and Clear, based on type 54S74 | |
9203/027 | 2 | Dual J-K Negative-Edge-Triggered Flip-Flop with Preset, based on type 54S113 | |
9203/028 | 3 | Dual J-K Negative Edge Triggered Flip-Flop with Preset and Clear, based on type 54S112 | |
9203/032 | 2 | Hex D-Type Flip-Flop with Clear, based on type 54S174 | |
9203/033 | 2 | Quadruple D-Type Flip-Flop with Clear, based on type 54S175 | |
9203/041 | 2 | Octal D-Type 3-State Positive Edge-Triggered Flip-Flop, based on type 54S374 | |
9204/029 | 2 | Synchronous 4-Bit Binary Counter with Synchronous Clear, based on type 54S163 | |
9204/044 | 2 | Presettable Divide-by-2 and Divide-by-5 Counter, based on type 54S196 | |
9306/024 | 2 | 4-Bit Parallel Access Shift Register, based on type 54S195 | |
9306/031 | 2 | 4-Bit Bidirectional Universal Shift Register, based on type 54S194 | |
9401/012 | 2 | Hex Inverter, based on type 54S04 | |
9401/015 | 2 | Quad 2-Input Positive NAND Buffer, based on type 54S37 | |
9402/004 | 2 | Dual 4-Input Positive NAND 50 Ohm Line Driver, based on type 54S140 | |
9408/007 | 2 | 8-to-1 Line Data Selector/Multiplexer, based on type 54S151 | |
9408/008 | 2 | 4-Line-to-1-Line Data Selector/Multiplexer, based on type 54S153 | |
9408/010 | 2 | Decoder/Demultiplexer, based on type 54S138 | |
9408/020 | 2 | Data Selector/ Multiplexer with 3-State Outputs, based on type 54S251 | |
9408/042 | 2 | Quad 2-Line-to-1 Line Data Selectors/Multiplexers, based on type 54S158 |