ECI 1-1

Closed

Thin film fuses
 (12 devices- Range:  0.14 -3.5A) 

Schurter, CH

ECI 1-2

Closed

Blue enhanced Photovoltaic Sensor 

AME (OSI) , N

--

ECI 1-3

Closed

Double Balance Mixer
(3 devices- Range:  0.7-10Ghz) 

OMMIC, F

--

ECI 1-4

Closed

Cascadable Amp
(5-250Mhz) 

Cobham (CTM) , F

--

ECI 1-5

Closed

Hybrid Double Balance Mixer
(2 devices  range 0.5-1500Mhz) 

Cobham (CTM) , F

--

ECI 1-6

Closed

Phased Lock loop
(3.5 Ghz Fractional N Freq Synthesizer) 

Peregrine, F

--

ECI 1-7

Closed

Hybrid PWM 

ETCA, B

--

ECI 1-8

Closed

European Schottky Diode (BES Process)

UMS , F

--

ECI 1-9

Closed

1553B Data Bus Products
(Remote Terminal & Transceiver ASICs) 

EADS , F

--

ECI 1-10

Closed

Image Reject Mixer
(750-2200 Mhz)

Cobham (CTM) , F

--

ECI 1-11

Closed

LEON 2 Microprocessor

ATMEL, F

--

ECI 1-12

Closed

Relays (TO5) ( 2 Devices T & TL)

REL (Deutsch), F

--

ECI 1-13

Closed

Power MOSFETs
(100 N-ch, 100V P-Ch)  

STM, I

Provision of EEE components

ECI 1-14

Closed

LVDS

STM, I

Provision of EEE components

ECI 2-1

Closed

Termination Insensitive Mixer 

Cobham (CTM), F

--

ECI 2-2

Closed

Phased lock loop   
(2 Devices 3.5Ghz Integer-N ) 

Peregrine, F

--

ECI 2-3

Closed

Digital Attenuator 

Peregrine, F

This activity is part of the ECI Phase 2 programme. Its objectives are to design, develop, manufacture and perform the ESCC qualification of two packaged MMIC Digital Attenuators. The MMIC process to be used will be preferably already space evaluated according to the ESCC requirements 2269010. The two types of DAT (Digital ATtenuator) will be packaged either directly by the selected foundry or by a validated European ATH (Assembly and Test House). The objectives of this activity will be achieved through the following steps:

1) Investigation and/or characterisation of existing technologies, processes and similar component types in order to help the technological process selection, the design trade-off analysis as well as the packages and assembly techniques to use for the two types of microcircuits to develop.
2) Description of the MMIC technological process, the design as well as the packages and assembly techniques selected for the components.
3) MMIC prototyping and breadboarding activities for the two types of DATs. The aim is to check that the performances are met at die level and after representative assembly of the two packaged MMICs.
4) Fabrication of at least 2 consecutive runs of functional components and packaging of the two DATs.
5) Performance of the ESCC Space evaluation of the DATs according to the requirements of the ESCC 2269010 followed by the performance of the ESCC qualification of the parts according to the ESCC 9010 requirements.

ECI 2-4

Closed

MMIC Digital phase shifter  (6-18GHz)

OMMIC , F

This activity is part of the ECI-2 programme. The objectives are to design, develop and validate for space application a GaAs MMIC 6-18 GHz phase shifter using an ESCC evaluated MMIC process from a European foundry. The 6-18 GHz MMIC phase shifter will be digitally controlled, with six cascaded bits (180°, 90°, 45°, 22.5°, 11.25°, 5.6°). These objectives will be achieved through the following steps:

1) Investigation and/or characterisation of existing technologies, processes and similar component types to help the technological process selection and design trade-off analysis for the component to develop.
2) Description of the MMIC technological process and the design selected for the component.
3) Fabrication of at least 2 consecutive runs of functional components.
4) Performance of the Space Validation of the phase shifter according to the requirements of the ECSS-Q-ST-60-12C.

ECI 2-5

Closed

MMIC "K" Band High Power Amp  

OMMIC , F

This activity is part of the ECI-2 programme. The objectives are to design, develop and validate for space application a GaAs MMIC K-Band High Power Amplifier (HPA) using an ESCC evaluated MMIC process from a European foundry. These objectives will be achieved through the following steps:

1) Investigation and/or characterisation of existing technologies, processes and similar component types in order to help the technological process selection and design trade-off analysis for the component to develop.
2) Description of the MMIC technological process and the design selected for the component.
3) Fabrication of at least 2 consecutive runs of functional components.
4) Performance of the Space Validation of the K-Band HPA according to the requirements of the ECSS-Q-ST 60-12C.

ECI 2-6

Closed

MMIC Wide Band Low Noise Amp

OMMIC , F

This activity is part of the ECI-2 programme. Its objectives are to design, develop and validate for space application a GaAs MMIC DC - 45 GHz wide band low noise amplifier (LNA) using an ESCC evaluated MMIC process from a European foundry. These objectives will be achieved through the following steps:

1) Investigation and/or characterisation of existing technologies, processes and similar component types in order to help the technological process selection and design trade-off analysis for the component to develop;
2) Description of the MMIC technological process and the design selected for the component;
3) Fabrication of at least 2 consecutive runs of functional components;
4) Performance of the Space Validation of the wide band LNA according to the requirements of the ECSS-Q-ST 60-12C.

ECI 2-7

Closed

MMIC "K" Band Power Amp
(17-24Ghz)

UMS/TAS, F

This activity is part of the ECI-2 programme. Its objectives are to design, develop and validate for space application a GaAs MMIC K-Band Power Amplifier (PA) using an ESCC evaluated MMIC process from a European foundry. These objectives will be achieved through the following steps:

1) Investigation and/or characterisation of existing technologies, processes and similar component types in order to help the technological process selection and design trade-off analysis for the component to develop;
2) Description of the MMIC technological process and the design selected for the component;
3) Fabrication of at least 2 consecutive runs of functional components;
4) Performance of the Space Validation of the K-Band PA according to the requirements of the ECSS-Q-ST 60-12C.

ECI 2-8

Closed

Triple balance Mixer (Descrete)

Cobham, F

This activity is part of the ECI-2 programme. Its objectives are to design, develop, manufacture and validate for space application an hybrid packaged Triple Balanced Mixer (TBM) using a European supplier. The hybrid mixer should be optimised to operate in the 2 to 18 GHz band with IF from 0.5 to 8 GHz. These objectives will be achieved through the following steps:

1) Investigation and/or characterisation of existing similar mixers in order to help the schottky technology, transformer components, package and fabrication techniques selection as well as the design trade-off analysis;
2) Description of the selected schottky process, transformer technology, package type and assembly process; design or redesign of specific component types in accordance with ECSS-Q-ST-60-05 requirements;
3) Procurement of active and passive chips, materials and piece parts for the fabrication of a first lot of functional microcircuits for Manufacturer Validation and Design Approval Testing; validation of the Hybrid Manufacturer and Design Approval Testing;
4) Fabrication of a second lot of functional hybrid mixers and performance of Lot Approval Testing according to the  ECSS-Q-ST-60-05 requirements.

ECI 2-9

Closed

Parallel fuses
(5 to 15A) 

Schurter , CH

ECI 2-11

Closed

Single point optical connectors

Diamond, CH

--

ECI 2-12

Closed

Low ESR tantalum capacitor 

AVX, CZ

ECI 2-13

Closed

Qualification of ATMEL 280K FPGA

ATMEL, F

The target of this activity is to define, manage, perform and complete the European Space Components Coordination (ESCC) evaluation of this 280Kgate FPGA device from ATMEL.

During this evaluation, the devices under test shall be extensively characterised and their margins determined in order to evaluate the capability of the ATF280F part for space applications. The evaluation of the component capabilities aims also to anticipate, as far as is possible, the component behaviour during qualification testing. As a result, during evaluation the objective shall be to overstress specific characteristics of the component concerned with a view to the detection of possible failure modes. Additionally, a detailed destructive physical analysis shall be performed to detect any design and/or construction defects which may affect the reliability of the component. All evaluation tests may in parallel indicate potential corrective improvements for reliability performance enhancement. 

ECI 2-16

Closed

Radiation hardened low-side MOSFET Driver

STM, (IT)

--

EEE3-1

Complete

Column attach process setup and evaluation   

ATMEL, FR

Set-up of solder columns attach on ceramic LGA and Evaluation.

EEE3-2

Contracted

Development /Qualification of Flip Chip for digital advanced components (65nm)

E2V, FR

QML certification of the process.

EEE3-3

Complete

Lead free finish of PCBs 

Astrium , FR

To analyse possible lead free finish and to perform a technology evaluation for compliance with new Reach and RoHS directives.

EEE3-4

Complete

Evaluation of the manufacture of mixed RF boards

 TAS, IT

Capability evaluation and prototype manufacturing of European mixed signal PCB.

EEE3-5

Cancelled

Evaluation of European Ultra Low Noise Phase Locked-Loop (PLL) Components 

Peregrine, FR

Assembly, testing and Qualification of two or more European PLLs components has been identified. The final objective of this activity is to list these PLLs in the ESCC QPL. These two European PLLs will constitute the Pin to Pin equivalent of the US products.

EEE3-6

Complete

Development and Space Validation of a European MMIC Wide Band Amplifier

OMMIC , FR

Design, Development and Validation for Space Application of a 0.2GHz-3.0GHz GaAs Wide Band Amplifier using an ESCC evaluated MMIC Process from a European Foundry. The aim of this activity is to replace the US MACOM MMIC MAAM02350.

EEE3-7

Complete

Development of a European MMIC Voltage Control Oscillator (VCO)

UMS, DE

Design, Development and Validation for Space Application of a 5.5 - 6.1GHz GaAs Heterojunction Bipolar Transistor (HBT) MMIC VCO using an ESCC evaluated MMIC Process from a European Foundry. The aim of this activity is to replace the US Hittite MMIC part HMC431LP4.

EEE3-8

Complete

ESCC Qualification of high voltage film capacitors, PET

Eurofarad, FR

ESCC qualification high voltage film capacitor, PET

EEE 3-9

Contracted

ESCC Evaluation and Qualification of Crystal oscillator

Rakon  (F & UK)

Develop an approved European source for XO crystal oscillator

EEE3-10

Contracted

ESCCQualification of new cable for continuous high temperature 

Axon Kabel

Evaluation and qualification of new cable able to sustain continuously high temperature (250-300C).

EEE3-11

Contracted

European source of 8-channel silicon phototransistors for optical encoders

Optoelectronica

The main goal of this frame of activities is to complete the manufacturing, the assembly of an 8 channel phototransistor, and initiate the product approval in conformity with the ESCC standard.

EEE3-12

Contracted

Industrialisation and ESCC evaluation of a Video Analog Signal Processor 

TESAT (DE)

The objective is to replace discrete component chains for CCD and CMOS detectors with VASP.

EEE3-13

Postponed

FPGA Tool Development 

FR

The aim of this activity is to ultimately complement the European offering and challenge the current US supply on all fronts by demonstrating the Radiation Hardening By Design (RHBD) of a highly integrated reprogrammable FPGA for space applications using a newly validated innovative FPGA architecture based on ex-Abound Logic IP, now with Mentor Metasystems, France. This new architecture provides a mix of programmable logic, and math and memory hard blocks, mapped on an advanced deep sub micron CMOS process, (baselined as the ST Microelectronics 65nm CMOS process developed under ESA TRP funding). This new FPGA will offer roughly 2.5M ASIC equivalent gates and will advantageously compete with its US competitors. This ECI activity will focus on the development of the SW and HW tools needed in addition to the actual FPGA HW IP redesign needed to adapt the existing IPs to the space requirements.

EEE3-14

Cancelled

ESCC Qualification of 450Kgate FPGA

--

ESCC evaluation of the SOI (Silicon On Insulator) ATMEL/OKI 450Kgate FPGA.

EEE3-15

Contracted

Technical Support of ESA IP Cores: (CCSDS File Delivery Protocol).

IDA, DE

This activity will provide a frame contract to obtain technical support for the user’s community (error investigations, code corrections, documentation improvements, evaluation of new cores, etc), as it becomes necessary, based on support contracts with IP originators.

EEE3-16

Cancelled

Development and ESCC Evaluation of a 32Mbit EEPROM 

ATMEL , FR

Development and ESCC evaluation of a radiation hardened 32Mbit EEPROM.

EEE3-17

Contracted

European LVDS driver development and ESCC Evaluation and Qualification

Aeroflex, SE

Define a common harmonised flow for the evaluation and qualification of mixed signal ASICs with a list of preferable foundries and assembly & test houses on mixed signal ASICs.

EEE3-18

Contracted

Assessment and characterization of Mixed Signal Technology

Sitael, IT

The objective is to develop European LVDS (Low Voltage Differential Signalling) transceivers (driver and receiver) compliant to ANSI/TIA/644 standard to be used in European Space Programs. ESD (electrostatic discharge) protection mechanism and tolerance vs common mode voltage shall be implemented ideally even improving the features of already existing devices. Design of LVDS drivers and receivers for Multi-point or Multidrop (e.g. for clock distribution) could be considered an optional second-level design activity.

EEE3-19

Postponed

Advanced qualification (Phase 3 ) for DSM ASIC technology & HSSL

--

To qualify STm Deep Sub-Micron process and HSSL developed under CNES strategic component plan and ESA TRP activities T501-301ED, Deep Sub Micron 65nm, high speed serial link and PLL (Phase 2) and T701-313ED, Deep Sub Micron 65nm rad hard library (Phase 2).

EEE3-20

Postponed

ESCC Evaluation and Qualification of a High-Speed Low Power European DAC.

E2V, FR

ESCC evaluation and qualification of a high-speed and low power European DAC offering.

EEE3-21

Cancelled

ESCC Evaluation and Qualification of a High-Speed ADC.

--

ESCC evaluation and qualification of a high-speed European ADC device.

EEE3-22

Complete

Radiation characterization of European commercial EEE components

TRAD, FR

To establish small support activities to evaluate COTS component for space applications in preparation of ECI next phases.

EEE3-23

Complete

Development/qualification of low power Ka band coaxial isolators/ circulators.

Cobham, FR

The objective of this activity shall be to develop and qualify low power coaxial isolators up to 32GHz, isolation equal to 23 dB, return loss equal to 23 dB and insertion loss of 0,5 dB.

EEE3-24

Contracted

Development/Qualification of high power coaxial isolators (S and C band).

Cobham, FR

The objective of this activity shall be to develop and qualify high power coaxial isolators in S and C band  with the following target performance:

• 150W in S band (100 MHz) and up to 120W in C band (300 and 500 MHz). 

• RL = 23dB, IL < 0.15dB.

EEE3-25

Postponed

ESCC Evaluation of a 0.13µm SiGe BiCMOS Technology

IHP , DE

--

EEE3-26

Contracted

European Radiation Hard PowerMOS Transistor for 100V - 150V Range: Technology and Products Development

Infineon , DE

--

EEE3-27

Closed

HAS2 wafer lot acceptance testing 

On-Semi , B

--

EEE3-28

Contracted

Development and ESCC Evaluation of Platinum Film Temperature Sensors, 

IST (CH)

--

EEE3-29

Contracted

Gan Epitaxi 

IQE, UK

--

EEE3-30

Contracted

RF MEM's High Q reconfigurable coaxial Filter

AURORA (ES)

--

EEE 401

Contracted

Selection, ESCC Eval and Qual of Capacitor and Resistors with extended operating temperature range for high power applications 

Alter, ES

The objective of this activity is to perform the ESCC evaluation/qualification of capacitors and resistors designed to withstand higher operating temperature.

EEE 402

Complete

ESCC Evaluation/Qualification of HV cable assembly

Reynolds, UK

The objective of this activity is to develop, evaluate and qualify, according ESCC requirements, High Voltage Cable Assembly (HV CA).

Targeting: HV Cable Assembly with:

• Rated voltage: > 5kV DC ^1,2

• Rated current: > 5 A DC ²

• Partial discharge free: < 5pC

¹⁾ 50% derating to ensure 2.5 kV max. nom. operating voltage

²⁾ higher current version is subject to upcoming market needs.

EEE 404

Contracted

ESCC Evaluation & Qualification of 150V Power-MOSFET SMD Package 

TESAT (DE)

The objective of this activity is to offer a broader portfolio of European sourced radiation hard PowerMOS transistors and to qualify a 150V PowerMOS technology in leaded SMD packages for space applications.

EEE 407

Contracted

European LVDS driver Development and ECSS Evaluation and Qualification - Phase 2 Test Vehicle 

Arquimea, ES

The objective is to prepare the prototype ASIC development of a new, Next Generation European rad-hard Digital Signal Processor (NG-DSP) based on the commercially proven DSP IP (ADSP-21469) from Analogue Devices (ADI) (originating and maintained by ADI team in India) that allows re-using the commercial Software Development Environment (maintained by ADI team in Ireland).

Target performance: at least 1000 MFLOPS ( FLoating Point operations / Sec).

EEE 408

Contracted

Space evaluation of ultra low noise processes for very high frequency applications 

OMMIC (FR)

The objective is to perform the space evaluation of a European ultra-low noise process based on the requirements provided in the ESCC Specification No 2269010.

EEE 409

Contracted

GREAT2 phase 3:  ( 2013 )ESCC Process Evaluation : GH 50-20 

UMS (DE)

The objective shall be to:

1) Validate performance and space suitability of UMS GH50_20 process.

2) Provide support towards further improvement of GH25_10 process in terms of performance and reliability and perform GH25_10 breadboard demonstration with large power bars to validate process stability and design rules.

3) Drafting of first generation ESCC standards for use of GaN technology in space.

4) Full space evaluation of GH50_20 process (starting 2013 and GH25_10 process starting in 2014).

EEE 410

Contracted

Space validation, ESCC of DFB Laser Module at 1.55 µm

Gooch & Housego (UK), UK

The objective is to perform a space validation of 1.55 um laser diode module following the expected ESCC laser diode module guidelines (in preparation).

The general performance specification for different application are:

-Emission wavelength of 1.55 um,

-MiniDIL or TOSA packages

-Pout=100 mW,

-Spectral width <500kHz.

EEE 411

Contracted

Space validation of Rad-Hard Erbium Optical Fibre Amplifier at 1.55 µm 

Constalex (GR) Gooch & Housego (UK), GR

The overall goal identified is to perform a space validation of rad-hard rare earth doped fibres in an optical amplifier at 1.55 µm addressing different type of space applications.

EEE 412

Contracted

CAPS (Contactless Angular Position Sensor) evaluation 

RUAG (CH)

The objective shall be the ESCC evaluation of monolithic CAPS (Contactless Angular Position Sensor) in accordance with ESCC 2269000 and EPPL listing.

EEE 413

Contracted

MEMS Reliability assessment 

HTA (VTT/Fraunhofer/ CSEM/CEA), Fi/DE/FR/CH

The objective shall be to develop a standardization methodology and standards for reliability assessment of MEMS products using commercial or ESA developed MEMS components.

EEE 414 

Contracted

High density PCB compatible with novel Flip Chip and High Pin Count Technologies

RUAG, SE

The objective is to design, manufacture and evaluate PCBs including HDI (High Density Interconnect) layers and high frequency signals (>6Ghz).

EEE 415

Cancelled

Evaluation and testing of potential German commercial  component technologies for space applications 

--

The objective shall be to evaluate and test German Commercial Off The Shelf (COTS) EEE component for space applications in anticipation of further development, evaluation and eventual ESCC qualification.

EEE 416

Closed

Radiation characterization of COTS for space applications 

Sieberdorf, AT

To establish small support activities ( via call off orders) to evaluate the radiation characterization of COTS component for consideration in future space applications.

EEE 417

Contracted

Reliability assessment/ evaluation/ characterization of commercial EEE parts/ JAXA qualified parts

Tyndal, Tyndall IRE

The objective is to perform independent reliability assessment, evaluation, and characterization of EEE parts developed either under ECI programme or through the JAXA qualified parts in support of potential ESCC entry into the European Preferred Parts Lists (EPPL) or European Qualified Parts List (EQPL).

EEE 418

Cancelled

ESCC Qualification of Video Analoque Signal Processor (VASP)

--

The objective shall be to procure the a full VASP wafer lot, assembly in accordance to Q60-05 (cat 2 manufacturer).Perform intensive rad test and ESCC chart F4 performance for Lot "Project type qualification".

EEE 419

Contracted

Advanced Cooling Technologies compatible with Novel Flip Chip and High Pin count technologies

Thermocore, UK

The objective shall be to design, manufacture and evaluate test pieces suitable to demonstrate the capabilities and performance of high thermal performance adhesives & materials that are suitable for space electronics applications.

EEE 420

Closed

ESCC Evaluation of 8 channel phototransistor for optical encoder with Hermetic glass lid

Optoi, OPTOI IT

The objective is to redeveloped within the frame of the on-going ECI phase 3 activity “European Source of 8 channel silicon phototransistors for optical encoders” a new package design with hermetic glass lid.

EEE 421

Contracted

Space validation of Rad-Hard co-doped Optical Fibre Amplifier at 1.55 µm for high power application (>1W)

GOOCH & HOUSEGO (UK)

The overall goal identified is to perform a space validation of rad-hard rare earth doped fibres in an optical amplifier at 1.55 µm addressing different type of space applications. This activity will focus with high power application (>1W) and therefore Erbium Ytterbium co-doped fibre should be selected for the validation.

Note : An independent activity to be started at the end of 2013 will address low power application (<1W) for which Erbium doped fibres are selected.

EEE 422

Contracted

Development, Prototyping and Electrical & Radiation Characterisation of a Rad-Hard High-Side MOSFET driver

STM (IT)

Key users will be surveyed in order to define the requirements of potential European customers and to identify possible improvements and trade-offs to the currently available US products.

A technology with proven radiation capability (TID and SEE) shall be selected and the product shall be designed with the objective to sustain at least 100krad and to SEL, SEU, SEB and SEGR free up to at least 60 MeV with limited SET.

The prototype devices will be diffused and assembled in hermetic packages and characterised electrically. Furthermore, the devices shall then be TID tested (high dose rate and/or low dose rate depending on the worst case scenario for the selected technology) and heavy ions tested (SEL, SEU, SEB, SEGR and SET) under conditions representative of the usage.

Note: Only prototypes shall be developed under this activity, a follow on  phase to perform the full ESCC evaluation and qualification of the MOSFET driver is envisaged.

EEE 423

 Intended

GREAT2 Phase 3.2 : Stabilisation, validation and space evaluation of a European 0.25µm gate length GaN  MMIC process.

UMS (DE)

The aim of this activity is to undertake additional industrial process stabilisation and a space evaluation of a European 0.25µm gate length GaN  MMIC process.

EEE424

 Complete

IP cores:  Full implementation of the CFDP protocol in the IP-Core. 

IDA , DE

--

EEE425

  Complete

Efficiency of the ECSS Process

ALTER, ES

--

EEE426

  Closed

Study for a Non-hermetic solution for Flip-Chip Products

E2V, FR

The objective of this activity is to study the Non-Hermetic flip chip technologies and show that the technologies identified and demonstrated shall be capable of qualification for space flight applications.

EEE428

 Contracted

Lot validation of 18x SpaceWire Router – GR718

AEROFLEX, (SE)

The objective of this activity is to lot validate the 18x SpaceWire router – GR718 and to manufacture a first flight batch. The GR718 has been developed in the frame of an ESA activity, covering design and manufacturing of the initial prototypes on a MPW run. The work also included evaluation board manufacturing and in-system functional validation of the part. The next step is to bring the part to flight production via lot validation, which is covered by this activity proposal.

EEE429

 Contracted

Rad-hard DDR physical interface and digital controller for Space-ST65nm

Cobham (SE)

The new Space-ST65nm rad-hard ASIC library allows for more complex designs with higher processing capabilities, such as NGMP, NGFPGA, NGDSP, advanced SoC ASICs, etc... These space components will often need to store large amounts of data in fast external memory. The preferred memory choice will often be DDR (Double Data Rate) SDRAM, driven by the commercial market. Currently the Space-ST65nm library lacks a DDR PHY and IOs.

The objective of this activity is to add the possibility of connecting a DDR memory to any design using the Space-ST65nm library, by defining, designing, prototyping, validating and characterizing a DDR PHY, IOs and controller that meet the needs of next generation deep submicron (DSM) standard space components as well as any other future space DSM System-on-Chips that require this capability.

EEE433

Contracted

Optical Fibre Temperature Sensor

EMXYS (ES)